Job Description

Location: Bangalore, India

Job Responsibilities:

• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.

Skills:

• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

We are looking for expertise on (Above 1 year):

• Understanding of memory architecture
• Experience in creating basic memory layouts from scratch
• Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
• Knowledge of compiler issues
• Understanding of reliability issues
• Simulation effects
• EMI (Electromagnetic Interference) considerations

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 3 - 10 years of experience.

Job Description

Location: Bangalore/Chennai/Hyderabad, India

Key Skills:

• Strong ability to read and understand legal and technical documents.
• Good at organizing and managing information in databases or spreadsheets.
• Clear writing and communication skills for creating reports and working with teams.
• Comfortable interacting with stakeholders and comparing different IP options.
• Basic knowledge of scripting or automation tools to help with data tasks.
• Attention to detail and ability to handle confidential information carefully.

Job Responsibilities:

• Read and review NDA and IP contract documents to capture important details and metadata.
• Organize and maintain IP information in databases or spreadsheets.
• Communicate with stakeholders globally to gather contract details, compare similar IPs.
• Use scripting or automation tools to make data collection and reporting easier.
• Prepare clear reports and summaries for management and other stakeholders.

Qualification:

• Bachelors or Masters in Electronics Engineering

Job Description

Location: Bangalore, India

Job Responsibilities:

• Proficiency in Layout Design and Physical Verification tools and methodologies.
• Strong understanding of Circuit Design and Analog principles.
• Experience with analog circuits and their layout techniques.
• Experience in layouts like CTLE, DFE, IDAC, PLL, LDO, BGR, TX.
• Knowledge of semiconductor design processes and industry standards.
• Attention to detail and problem-solving abilities.
• Practical experience in Serdes/DDR layout design is highly advantageous

Education & Experience:

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 4 - 5 years of experience on serdes/DDR layout experience. Preferably worked on TSMC 7NM, 5NM.

Job Description

Location: Shanghai, China

Job Responsibilities:

• Support post-silicon bring up, validation, and new silicon features characterization
• Support post-silicon perf/power characterization
• Set up x86 and SoC platforms for electrical and functional validation
• Execute test plan on engineering systems that involve stress testing, functional testing, power measurements, etc.
• Collect data from large number of systems, verify logs, identify failures/marginalities/outliers and report to the function owner
• Basic scripting that includes modifying existing scripts where applicable

Education & Experience:

• BS or MS in EE, CE, CS, Systems Engineering
• 2 - 3 years of meaningful PC HW experience
• Hands-on experience with silicon bring up, frequency and power characterization, Tester to System correlation, lab tools (oscilloscopes, multimeters, DAQ)
• Experienced with Windows, and Linux. Exposure to BIOS, drivers, and other software applications
• Experience with Perl, C/C++, tool and script development, Windows and Linux OS is a plus

Job Description

Location: Bangalore, India

Job Responsibilities:

• Responsible for conducting end-to-end Signal integrity simulations for the High speed IO channels(>=112G) to meet the timing and Voltage specifications.
• Responsible for modeling of the Package and board for the channel.
• Optimization of the Package and board design for enabling the best channel margins.
• Provide inputs for the cross functional teams (Silicon, Package and Board).
• Driving the materials and connectors/cables for the platform.

Qualifications & Experience:

• More than 10 years of industry experience in Signal integrity modeling and Analysis for Package and platform.
• Prior experience working on the PCIe Gen6 or ethernet 112G interfaces.
• Strong Fundamental in transmission line theory and EM simulations tools.
• Understanding of the latest PCIE and Ethernet standards.
• Understanding of the various connector and Cable technologies (CDFP, QSFP, OSFP, Backplane, DAC, AEC, AOC).
• Experience with Signal integrity modeling and simulations tools (like ADS SI/RFPRO, HFSS).
• Experience with Signal integrity analysis tools (like ADS, HSPICE, Sigrity).
• Understanding of the Package and PCB Stack-up.

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is seeking a Design Verification Engineer to ensure functional correctness and robustness of mixed-signal SoC subsystems, including peripheral interfaces, audio blocks, and power management logic. You will work closely with RTL, architecture, and system teams to build comprehensive verification environments, drive coverage, and ensure first-pass silicon success.

Key Responsibilities

• Verification Architecture & Planning
  • Define and execute verification strategy for subsystems: SPI, UART, I2C, Audio interfaces (I2S, TDM), Power management digital controllers
  • Develop test plans with full functional and corner-case coverage
  • Identify verification risks and coverage gaps early
• UVM-Based Verification Development
  • Build and maintain UVM/System Verilog testbenches
  • Develop reusable VIPs and monitors, scoreboards and checkers, constrained-random stimulus
  • Implement protocol-aware verification components
• Coverage & Quality
  • Drive: functional coverage, code coverage (line, toggle, FSM)
  • Ensure closure of coverage goals and assertion checks
  • Track and report verification metrics
• Debug & Validation
  • Debug RTL issues and root-cause failures
  • Work closely with RTL engineers on bug fixes and improvements
  • Support post-silicon validation with test reuse where applicable
• System-Level Verification
  • Contribute to SoC-level verification: subsystem integration scenarios, firmware-driven tests
  • Validate interactions across clock, reset, and power domains

Required Qualifications

• 5–12 years of DV experience in SoC/subsystem verification
• Strong expertise in System Verilog and UVM
• Functional coverage and assertions (SVA)
• Experience verifying AMBA protocols (AXI/AHB/APB)
• Experience verifying peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is looking for a Physical Design Engineer to implement high-quality, low-power analog and digital blocks and subsystems within mixed-signal SoCs. You will be responsible for taking RTL through synthesis, place & route, and signoff, ensuring timing, power, and area targets are met. Past experience on TSMC, 22nm and below nodes. This role requires strong collaboration with RTL, DV, and analog teams to deliver silicon-ready designs.

Key Responsibilities

• Implementation Flow Ownership
  • Drive full physical design flow: Synthesis, Floorplanning, Place and route (PnR), Clock tree synthesis (CTS), Physical verification and signoff
  • Optimize for timing, power, and area (PPA)

Required Qualifications

• 5–12 years of physical design experience having worked on TSMC 22nm and below nodes
• Strong expertise in Synthesis and PnR tools (e.g., Cadence/Synopsys flows), STA and timing closure
• Experience with Advanced nodes and SoC integration, Multi-clock, multi-power domain designs

Preferred Qualifications

• Experience with mixed-signal SoC floorplanning
• Familiarity with IR drop, EM, signal integrity analysis
• Exposure to ARM Cortex-M or RISC-V based SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Qualifications & Experience:

• More than 10+ years of experience in the flip chip BGA package design.
• Experience working on the Large Formfactor, high layer count designs, Stack-up definition, Bump and ball map definition, Package outline drawings.
• Very good understanding of the package design rules as well as design for manufacturing and successful tape out of multiple designs.
• Knowledge of Package level signal integrity and power integrity.
• Worked on High speed Serdes (PCIE Gen6, 112-224 G Ethernet) and memory interface like DDR5, LPDDR and HBM.
• Mentor Xpedition experience is preferred.

Job Responsibilities:

• Responsible for the package design of the Leading edge AI products for Tsavorite.
• Responsible for the feasibility studies for the new IP definition and Package design concepts.
• Owning the substrate layout design from start to end and taping out multiple products.
• Co-design between Silicon, package and board.
• Collaborate closely with the Signal integrity, power integrity leads, PCB design, Mechanical and thermals to optimize the design to meet the product requirements.
• Interface with the OSAT/Packaging suppliers to understand the design rules, review the package design, meet DFM requirements and Documentation of BOM.

Job Description

Location: Chandler, US or Chennai, India

Experience: 5–8 years

Job Description

CAD team is looking for highly analytical and detail-oriented Application Engineer, having an understanding on ASIC Design and building blocks used in such a design. This role involves capturing and managing IP metadata, comparing IP offerings, and collaborating with business unit leaders to gather IP information. They would need to review Non-Disclosure Agreements (NDAs) and Intellectual Property (IP) contract documents. Scripting knowledge is an added advantage for automating data extraction and reporting processes.

Key Skills

• Strong knowledge on ASIC Design flow and IPs that get used in chip design.
• Strong ability to read and understand legal and technical documents.
• Good at organizing and managing information in databases or spreadsheets.
• Clear writing and communication skills for working with remote teams / customers.
• Comfortable interacting with stakeholders and comparing different IP options.
• Basic knowledge of scripting or automation tools to help with data tasks.
• Attention to detail and ability to handle confidential information carefully.

Job Responsibilities

• Organize and maintain IP information in databases or spreadsheets.
• Communicate with stakeholders globally to gather contract details, compare similar IPs.
• Read and review NDA and IP contract documents to capture important details and metadata.
• Use scripting or automation tools to make data collection and reporting easier.
• Prepare clear reports and summaries for management and other stakeholders.

Qualification

• Bachelors or Masters in Electronics Engineering with 5-8 years of experience

Job Description

Location: Bangalore, India

Experience: 5–15 years

Role Overview:

In this role, you will be responsible for Gate-Level Simulation (GLS) verification of complex SoCs across IP, subsystem, and full-chip levels. The focus will be on validating timing correctness, reset/power behavior, clock-domain crossings, and ensuring functional equivalence between RTL and gate-level implementations. The task list includes, but is not limited to, GLS testplan development, environment adaptation, SDF back-annotation, regression execution, and debug of timing and initialization issues at various design hierarchies.

Roles And Responsibilities:

• Partner with RTL Design, Synthesis, and Physical Design teams to understand timing constraints, clocking architecture, reset strategy, and low-power intent.
• Develop comprehensive GLS test plans covering timing scenarios, reset/initialization sequences, power-aware behavior, and corner-case conditions across IP, subsystem, and chip levels.
• Adapt and enhance existing RTL verification environments for gate-level simulations, including handling X-propagation, timing checks, and initialization differences.
• Perform SDF back-annotation and validate setup/hold timing, clock skew, and multi-cycle/false path behavior.
• Execute GLS regressions (zero-delay, unit-delay, full-timing) and analyze failures related to timing violations, metastability, and unknown (X) propagation.
• Debug complex GLS issues including race conditions, reset sequencing problems, clock-domain crossing (CDC) issues, and mismatches between RTL and netlist behavior.
• Validate low-power features such as clock gating, power gating, retention, and isolation in gate-level environments.
• Perform equivalence-oriented validation between RTL and gate-level simulations and support signoff readiness.
• Collaborate with DFT teams to validate scan insertion, ATPG patterns, and test modes in gate-level environments.
• Support post-silicon bring-up by correlating GLS results with silicon behavior and debugging initialization/timing-related issues.
• Track and communicate DV progress using metrics such as GLS coverage, regression status, bug tracking, and closure reports.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science with 5 to 15 years of relevant experience
• Strong understanding of digital design fundamentals, timing concepts (setup/hold, clock skew, jitter), and static timing analysis (STA)
• Proven expertise in Gate-Level Simulation (GLS) including SDF back-annotation, timing simulation modes, and debug of timing-related issues
• Strong knowledge of clock-domain crossing (CDC), reset-domain crossing (RDC), and metastability concepts
• Hands-on experience with SystemVerilog/UVM and/or C/C++ based verification methodologies
• Experience with industry-standard simulation and debug tools (Questa, Visualizer)
• Familiarity with constrained-random verification, assertions, and functional/code coverage methodologies

Preferred Qualifications:

• Experience in adapting RTL UVM environments for GLS with focus on X-propagation handling and timing awareness
• Hands-on expertise in GLS across IP, subsystem, and full-chip levels for complex SoCs
• Familiarity with low-power verification methodologies (UPF/CPF), including retention, isolation, and power state transitions
• Experience working with synthesis and STA tools (e.g., PrimeTime) and understanding of timing closure flows
• Exposure to DFT/scan/ATPG validation and test mode verification in GLS
• Experience with scripting and automation for GLS regression management (Python/Perl/Shell)
• Understanding of equivalence checking concepts and flows (RTL vs gate-level)
• Strong debugging skills for complex gate-level issues and ability to drive closure across cross-functional teams
• Strong drive for DV infrastructure automation and signoff quality improvements

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science or related field

Job Description

Location: Bangalore, India

Experience: 5–15 years

Role Overview:

In this role, you will be working on high-performance GPU cores and graphics subsystems at block and SoC levels. The responsibilities include verification of GPU IP in both standalone and integrated environments, ensuring functional correctness, performance validation, and interoperability across system components. The task list includes, but is not limited to, testplan development, environment development, checker/scoreboard creation, test execution, and debug at IP, subsystem, and SoC levels.

Roles And Responsibilities:

• Partner with Architects and RTL Design teams to understand GPU architecture, graphics pipeline, and system-level requirements.
• Formulate comprehensive test and coverage plans aligned with GPU architecture and micro-architecture (compute, graphics, memory hierarchy, and interconnect).
• Develop verification environments with reusable components such as BFMs, drivers, monitors, scoreboards, assertions, and coverage models.
• Build and integrate GPU-specific verification components including traffic generators, shader/compute workload generators, and memory models.
• Create verification plans and develop testbenches tailored to GPU IP blocks (e.g., shader cores, command processor, memory subsystem) and full GPU subsystem integration.
• Execute verification plans including design bring-up, DV environment setup, regression execution, feature validation, and debug of complex functional and performance issues.
• Perform integration verification of GPU IP with system interconnects (AXI/NoC), memory subsystems (DDR/HBM), cache hierarchies, and power/clock domains.
• Validate graphics and compute workloads, scheduling, coherency, bandwidth utilization, and corner-case scenarios.
• Support post-silicon bring-up, validation, and debug activities, including correlation with pre-silicon results.
• Track and communicate DV progress using key metrics such as testplan status, bug tracking, and functional/code coverage.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science with 5 to 15 years of relevant experience
• Strong architecture knowledge of GPU design, including graphics pipeline and memory subsystems
• Strong expertise in System Verilog/UVM methodology and/or C/C++ based verification with 5+ years of hands-on experience in IP/subsystem/SoC level verification
• Hands-on experience with industry-standard simulation and debug tools (Questa, Visualizer)
• Experience with constrained-random verification, functional coverage, and assertion-based verification methodologies

Preferred Qualifications:

• Experience in developing UVM-based verification environments from scratch for complex GPU or high-performance compute IPs
• Hands-on expertise in GPU IP verification
• Strong knowledge of AMBA protocols (AXI/AHB/APB) and NoC-based system integration
• Experience with performance verification, profiling, and bottleneck analysis in GPU subsystems
• Experience with cache coherency, virtualization, and multi-core/multi-engine GPU systems
• Exposure to post-silicon validation, lab bring-up, and debug

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science or related field

Job Description

Location: Bangalore, India

Experience: 5–15 years

Role Overview:

In this role, you will be working on high-speed USB controllers (USB 3.x, USB4) and subsystem integration at block and SoC levels. The responsibilities include verification of USB IP in standalone and integrated environments, ensuring compliance with protocol specifications, and validating interoperability across different system components. The task list includes, but is not limited to, testplan development, environment development, checker/scoreboard creation, test execution, and debug at IP, subsystem, and SoC levels.

Roles And Responsibilities:

• Partner with Architects and RTL Design teams to understand USB architecture, integration requirements, and system-level use cases.
• Develop comprehensive test plans and coverage models aligned with USB specifications and micro-architecture (USB 3.x, USB4).
• Build and enhance verification environments using reusable components such as BFMs, drivers, monitors, scoreboards, assertions, and protocol checkers.
• Develop and integrate USB VIPs, host/device models, and system-level components for end-to-end verification.
• Create verification plans and develop testbenches tailored to USB IP, subsystem integration, and SoC-level validation.
• Execute verification plans including design bring-up, environment setup, regression execution, feature validation, and debug of complex protocol and integration issues.
• Perform integration verification of USB IP with interconnects (AXI/AHB/APB), PHY/SerDes, power management, and other SoC components.
• Validate USB protocol compliance, link training, enumeration, power states, and error handling scenarios.
• Support post-silicon bring-up, validation, and debug activities including lab correlation with pre-silicon results.
• Track and communicate DV progress using metrics such as testplan completion, bug tracking, and functional/code coverage.

Requirements:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science with 5 to 15 years of relevant experience
• Strong architecture and protocol knowledge in USB standards (USB 3.x, USB4), including link, transaction, and power management layers
• Good understanding of USB PHY/SerDes interfaces, PIPE interface, and high-speed signaling basics
• Strong expertise in System Verilog/UVM methodology and/or C/C++ based verification with 5+ years of hands-on experience in IP/subsystem/SoC level verification
• Hands-on experience with industry-standard simulation and debug tools (Questa, VCS, Verdi/Visualizer)
• Experience with constrained-random verification, functional coverage, and assertion-based verification methodologies

Preferred Qualifications:

• Experience developing UVM-based verification environments from scratch for complex IPs
• Hands-on expertise in USB controller verification in host, device, and OTG/dual-role modes
• Experience with USB compliance testing, interoperability testing, and certification requirements
• Familiarity with industry-standard USB VIPs (e.g. Avery) and building protocol-specific stimulus
• Strong knowledge of AMBA protocols (AXI/AHB/APB) and their integration with USB subsystems
• Experience with low-power verification (power states, clock gating, retention) in USB subsystems
• Exposure to post-silicon validation, lab bring-up, and debugging using analyzers/protocol tools

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering/Computer Engineering/Science or related field

Job Description

Location: Bangalore, India

Experience: 10+ years

Role Overview:

Seeking Senior PCB Layout Designer who will support the physical design of complex, high-speed PCBs.

Key Responsibilities:

• Layout for multilayer boards (>10 layers) supporting High speed Serdes Interface (up to 224G) and High power solutions (KW)
• Create and maintain footprints in the library and validate
• Feasibility studies for various system and board configurations and identifying the tradeoffs
• Perform constraint-driven routing of critical nets — length matching, differential pair tuning, via stub minimization
• Design for DFM/DFT

Required Qualifications:

• 10+ years of professional PCB layout experience on high-speed Serdes designs and high power
• Deep proficiency in Cadence Allegro tool
• Proven hands-on experience defining the HDI stack-up and designing HDI boards with blind/buried vias
• Demonstrated expertise in symbol and footprint generation from Scratch
• Solid understanding of SI design: Breakout, Via stubs, Loss, xtalk and impedance requirements
• Solid understanding of PDN design: decoupling solution, Power stage and inductor design, Isolation requirements
• B.S. in Electrical Engineering, Electronics Technology, or equivalent demonstrated experience

Preferred Qualifications:

• Worked on PCIe Gen6/7 and 112G/224G Ethernet interfaces
• Understanding of the various connector solutions for high speed Serdes
• Hands-on experience working from the start to the finish of the PCB design

Tools:

• Cadence Allegro, Siemens Xpedition Schematic

Qualification:

• Bachelor's degree in Electrical Engineering, Electronics Technology, or equivalent demonstrated experience

Job Description

Location: Santa Clara, USA

Experience: 3–10 years

Role Overview

Manufacturing Product Engineer Focus: PCBA Assembly & Production Support. This is a technical implementation role focused on the physical assembly and maintenance of production hardware. You will be responsible for executing mechanical and electrical assembly tasks, maintaining the fixtures used on the line, and ensuring all work follows established documentation.

Core Responsibilities

Technical Assembly & Maintenance

• Perform mechanical assembly of hardware units following specific build sequences.
• Ability to execute PCBA rework, soldering, and component-level modifications as required.
• Must understand context of PCBA assembly, packages, processes.
• Maintain, troubleshoot, and perform routine repairs on assembly fixtures and production tooling.
• Use electrical engineering knowledge to perform board-level testing and troubleshooting during integration.

Documentation & Process Adherence

• Follow and verify Standard Operating Procedures (SOPs) and detailed Work Instructions.
• Assist in drafting and updating technical documentation for assembly processes.
• Document all rework, assembly anomalies, and fixture maintenance logs accurately.

Production Operations

• Move material and hardware through the assembly stages.
• Identify and report practical issues in the assembly process to the full-time engineering staff.
• Support the setup and teardown of production lines and test stations.

Requirements & Qualifications

• Experience: Hands-on experience in a hardware manufacturing or lab environment.
• Technical Skills: Proficiency in mechanical assembly and PCBA rework/soldering.
• Electrical Knowledge: Understanding of electrical circuits and the ability to read schematics.
• Tooling: Ability to use hand tools and rework stations, and maintain mechanical fixtures.
• Knowledge of IPC standards for soldering and rework.
• Familiarity with inventory tracking or shop-floor management software.

Qualification:

• Bachelor's degree in Electrical Engineering, Electronics, Manufacturing Engineering, or a related field.

Job Description

Location: Hyderabad, India

Experience: 7–25 years

Key Responsibilities

Verification Architecture & Planning

• Define and execute verification strategy for subsystems:
  • SPI, UART, I2C
  • Audio interfaces (I2S, TDM)
  • Power management digital controllers
• Develop test plans with full functional and corner-case coverage
• Identify verification risks and coverage gaps early

UVM-Based Verification Development

• Build and maintain UVM/System Verilog testbenches
• Develop:
  • Reusable VIPs and monitors
  • Scoreboards and checkers
  • Constrained-random stimulus
• Implement protocol-aware verification components

Coverage & Quality

• Drive:
  • Functional coverage
  • Code coverage (line, toggle, FSM)
• Ensure closure of:
  • Coverage goals
  • Assertion checks
• Track and report verification metrics

Debug & Validation

• Debug RTL issues and root-cause failures
• Work closely with RTL engineers on bug fixes and improvements
• Support post-silicon validation with test reuse where applicable

System-Level Verification

• Contribute to SoC-level verification:
  • Subsystem integration scenarios
  • Firmware-driven tests
• Validate interactions across clock, reset, and power domains

Required Qualifications

• 7–25 years of DV experience in SoC/subsystem verification
• Strong expertise in:
  • System Verilog and UVM
  • Functional coverage and assertions (SVA)
• Experience verifying:
  • AMBA protocols (AXI/AHB/APB)
  • Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Santa Clara, USA

Experience: 6–15 years

Job Description

Design Execution

• Take ownership of schematic modifications, component second sourcing, and BOM optimization for existing multi-rail, high-power PCIe accelerator cards.

DVT & Debug

• Lead the hands-on hardware bring-up and system-level debug of Corsair boards.
• Identify and resolve root causes for PCIe Gen5 link instability and power transient issues.

Power & Signal Integrity

• Execute detailed SI/PI validation plans.
• Use high-speed oscilloscopes, VNA/TDR, and BERTs to verify 32Gbps+ signals and low-voltage, high-current PDN performance.

Cross-Functional Sync

• Act as the primary technical point of contact for Thermal and Mechanical teams to resolve layout-level integration issues during the NPI (New Product Introduction) phase.

DFx Implementation

• Perform design reviews focused on DFM/DFT/DFA to ensure high-yield production readiness for upcoming manufacturing runs at Wistron.

Technical Documentation

• Generate comprehensive hardware validation reports and bring-up guides to enable seamless handoffs to the software and validation teams.

Qualification:

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.

Job Description

Location: Santa Clara, USA

Focus: Hardware / AI Infrastructure Operations

We are seeking a highly organized and proactive Quality Engineering Contractor to support our full-time Quality and Reliability Engineering team. This is a facilitator and implementer role focused on executing Quality Management System (QMS) initiatives and managing the operational logistics of our hardware quality programs.

The Mission: You are the "Force Multiplier." Your objective is to handle the tactical implementation, documentation, and material coordination that allows the senior engineering team to focus on high-level strategy and architectural reliability.

Core Responsibilities

• QMS Implementation & Maintenance:
  • Assist FTE engineers in developing and documenting QMS processes, including Control Plans, Work Instructions, and process flows.
  • Maintain quality documentation and records to ensure audit readiness.
  • Track open action items and Corrective Actions (CAPA), ensuring no threads are lost across workstreams.
  • Support internal audits by collecting evidence and organizing findings.
• Internal RMA & Failure Analysis Support:
  • Process and track internal RMAs, maintaining accurate records of returns and dispositions.
  • Coordinate failure analysis (FA) workflows, tracking requests through closure and summarizing results.
  • Surface trends and patterns in defect data to the engineering team via regular reporting.
• Material & Logistics Coordination:
  • Coordinate physical material movement: returns, holds, quarantine, and sample management.
  • Execute cycle counts and reconcile inventory discrepancies for hardware assets, such as Units Under Test and hold inventory.
  • Liaise with Operations and Warehouse teams to ensure timely material handling.

Requirements & Qualifications

• Experience: 3–6 years in quality engineering, quality operations, or technical hardware roles.
• QMS Knowledge: Familiarity with ISO 9001 or similar quality frameworks.
• Hardware Context: Experience with PCBA or systems-level hardware environments, such as PCIe cards or server infrastructure.
• Detail Oriented: Proven ability to manage multiple open threads and maintain high data integrity.
• Communication: Strong ability to collaborate across Engineering, Operations, and Program Management.

Preferred Skills (Nice to Have)

• ASQ Certification, such as CQE or CQA.
• Familiarity with quality tools: 8D, 5-Why, and basic Statistical Process Control (SPC) concepts.
• Familiarity with PLM tools like Agile/Arena.

Job Description

Location: Santa Clara, USA

Focus: PCBA Assembly & Production Support

This is a technical implementation role focused on the physical assembly and maintenance of production hardware. You will be responsible for executing mechanical and electrical assembly tasks, maintaining the fixtures used on the line, and ensuring all work follows established documentation.

Core Responsibilities

• Technical Assembly & Maintenance:
  • Perform mechanical assembly of hardware units following specific build sequences.
  • Ability to execute PCBA rework, soldering, and component-level modifications as required.
  • Must understand context of PCBA assembly, packages, and processes.
  • Maintain, troubleshoot, and perform routine repairs on assembly fixtures and production tooling.
  • Use electrical engineering knowledge to perform board-level testing and troubleshooting during integration.
• Documentation & Process Adherence:
  • Follow and verify Standard Operating Procedures (SOPs) and detailed Work Instructions.
  • Assist in drafting and updating technical documentation for assembly processes.
  • Document all rework, assembly anomalies, and fixture maintenance logs accurately.
• Production Operations:
  • Move material and hardware through the assembly stages.
  • Identify and report practical issues in the assembly process to the full-time engineering staff.
  • Support the setup and teardown of production lines and test stations.

Requirements & Qualifications

• Experience: Hands-on experience in a hardware manufacturing or lab environment.
• Technical Skills: Proficiency in mechanical assembly and PCBA rework/soldering.
• Electrical Knowledge: Understanding of electrical circuits and the ability to read schematics.
• Tooling: Ability to use hand tools and rework stations, and maintain mechanical fixtures.
• Knowledge of IPC standards for soldering and rework.
• Familiarity with inventory tracking or shop-floor management software.

Job Description

Location: Bangalore

Key Responsibilities

• Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production.
• Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets.
• Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness.
• Define and implement test strategies for analog and mixed-signal IPs, including DFT hooks, wrappers, and test mode integration.
• Create test patterns and perform ATPG analysis to ensure test coverage goals are met.
• Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams.
• Automate and optimize DFT flows and scripting for scalability and efficiency.

Required Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering or related discipline.
• Minimum 10 years of hands-on experience in DFT with successful tapeouts.
• Strong knowledge of scan insertion, scan compression, transition fault (at-speed) testing, and boundary scan (IEEE 1149.1/1500).
• Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired.
• Experience with ATPG tools, test coverage analysis, and test pattern generation.
• Solid understanding of DFT for AMS blocks, including challenges in testability of analog circuits.
• Familiarity with scripting languages (TCL, Perl, Python) for automation.
• Good understanding of STA constraints for DFT and impact on synthesis and physical design.
• Proven experience in silicon debug and production test support.

Job Description

Location: Bangalore

Who You'll Work With

Working as part of the hardware team. Supporting hardware and software teams with various lab activities. You will also work closely with the procurement, IT and facilities team to maintain an operational lab.

What You'll Do

Lab engineers will be responsible for hardware design and test lab upkeep, procurement, maintenance, rework and bring-up support as their primary role. They will also look after AMC for equipment and calibration of test equipment. Support any internal or external lab audits.

Key Responsibilities

• Perform rework on networking products prototypes for ICs and discrete components with high quality and reliability.
• Test and troubleshoot proto boards under Hardware lead's guidance.
• Maintain well equipped and fully functional hardware rework stations at all times.
• Coordinate the Calibration and upkeep of all lab test and measurement equipment through 3rd party or OEM.
• AMC and repair for all EDVT test chambers.
• Participate in lab audits and implement any necessary corrective actions.
• Maintain inventory of all hardware test equipment, optical modules and prototypes.
• Collaborate with IT teams to implement any required security update and ensure all lab equipment with network access compliant to IT requirements.
• Co-ordinate rework activity with 3rd party lab or CM if in-house rework is not feasible.
• Procurement of lab consumables in timely manner.
• Work with logistics co-ordinator, external test partners and facilities team to ensure SEZ compliance.
• Strict adherence to safety, industry certifications, and environmental compliance regulations.

Qualifications

• Diploma in electrical, electronics or certification course in electronics and electrical repair is preferred.
• A minimum of 7 years of experience as lab technician, or lab engineer is required.
• Ability to perform complex re-work on networking hardware is a must have skill.
• Hands-on experience of using X-ray machines, BGA rework machine is a big plus, at minimum understanding of the BGA rework process is required.
• Excellent verbal and written communication is required.
• Ability to maintain clear and traceable records for inventory with web-tool is required.
• Basic understanding of networking and ability to configure network switches, Servers is needed.

Job Description

Location: Bangalore

What You Will Do

Get ready to dive into an exhilarating journey as you work on the bring-up, validation, and debugging of a groundbreaking interference accelerator chip/chiplets! Here's what you can look forward to:

• Work on chip(s) bring up, validation and debug of cutting-edge interference accelerator chiplet. This includes cutting-edge technology: test and validate high-speed serial protocols like PCIe Gen5, high-speed memory interfaces such as LPDDR5, and die-to-die chiplet interconnect blocks.
• Innovate and execute: Create and implement comprehensive test bring-up and validation plans alongside your dynamic team, develop automated randomization of software/firmware kernel functions and logging instrumentation in conjunction with self-checking post processors.
• Craft impactful test scripts: Develop test scripts and embedded firmware functions for host systems that will test and validate aspects of our high-speed interfaces, including PCIe, LPDDR, and D2D, pushing the boundaries of what's possible.
• Equip your workspace: Collaborate with your team to procure and acquire the latest lab equipment, ensuring you have the tools needed to succeed.
• Collaborate and conquer: Work hand-in-hand with hardware, software, and operations teams on exciting challenges such as ATE tests and hardware/software debugging, fostering a spirit of teamwork and innovation.

What You Will Bring

• BS/MS in Electrical/Computer Engineering with 5+ years industry experience working with high performance SoC.
• Familiarity with high speed serial protocol (such as PCIe Gen3/4/5) and/or high speed external memory technology (such as LPDDR3/LPDDR4/LPDDR5 and/or high speed I/O standards).
• Excellent debugging verbal and written communication skills.
• Capable of working effectively across cross functional organizational boundaries.

Job Description

Location: Bangalore

Key Responsibilities

• Generate PLIBs and Drivers using in-house AI tools.
• Develop drivers manually in C for select peripherals.
• Review ASPICE SWE1-SWE6 documents and suggest improvements.
• Develop example applications and documents for the drivers.
• Perform Hardware testing.

Eligibility

• Excellent C and Python programming skills.
• Excellent Microcontroller and peripherals working experience.
• 4-5 years of development experience.
• Knowledge of CMSIS architecture and API definition.

Job Description

Location: Chennai

Key Responsibilities & Requirements

• Experience in Embedded firmware development.
• Experience in MISRA C, CERT C, and CWE (Common Weakness Enumeration) guidelines and making embedded firmware codebases compliant to these coding standards.
• Experience with I2C and UART is good to have.

— OR —

• Experience in Embedded firmware development with either NVMe SSD controllers (either SSD host driver or SSD device FW) or PCIe Gen4/Gen5 devices; One of these is a must.
• Experience in working with VMware ESXi environment is good to have.

Job Description

Location: Bangalore

Key Responsibilities

• Partitioning for ATPG and hierarchical approaches.
• ATPG compression and serialization.
• RTL-Scan insertion and design rule fixing.
• Expertise in Memory BIST including Memory Repair, In-System Test (IST) for Memories from Implementation to Verification and Silicon Debug.
• Experience on Boundary Scan and writing DFT mode constraints for IP's and providing the timing feedback to STA team for DFT modes.
• Experience on DFT RTL generation and Integration with RTL level QC checks like Spyglass LINT, Spyglass DFT and Fishtail.
• Familiar with IEEE1149.1, IEEE1500 and IEEE1687 standards.
• Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
• Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis.
• Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
• Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE.
• Having experience with state-of-the-art, industry-standard DFT tools.
• Being hands-on from the "nitty-gritty" details to high-level planning.

Minimum Qualifications

• BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field.
• 7+ years of experience with DFT technologies, including scan test and MBIST.
• Experience with a hardware description language such as Verilog, System Verilog, or VHDL.
• Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.).
• Ability to work well in a diverse team environment.
• Experience delivering detailed technical documentation.

Job Description

Location: Bangalore

We are looking for a strong CAD & Flow Automation Engineer to take ownership of critical design automation and DFT infrastructure. The ideal candidate is highly capable, self-driven, technically versatile, and able to ramp quickly in a fast-moving environment.

Core Requirements

• Strong Python and TCL scripting skills.
• 6+ years of experience building and maintaining CAD/design automation flows.
• Hands-on experience with flow setup/automation in at least one of the following areas:
  • DFT
  • PrimePower
  • LEC
  • Virtuoso
  • Voltus / RedHawk

Preferred Experience

• Synopsys DFT flow experience.
• Power and signoff flow automation.
• Tool installation, configuration, and infrastructure support.
• Virtuoso/SI2 scripting experience.

Key Responsibilities

• Own and maintain design and DFT flows.
• Develop scalable automation infrastructure and scripting solutions.
• Support DFT-related flows including SPF extraction, ATPG pattern generation, comp mode WRP, etc.
• Support EDA tool deployment, integration, and user enablement.