Job Description

Location: Bangalore, India

Job Responsibilities:

• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.

Skills:

• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

We are looking for expertise on (Above 1 year):

• Understanding of memory architecture
• Experience in creating basic memory layouts from scratch
• Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers
• Knowledge of compiler issues
• Understanding of reliability issues
• Simulation effects
• EMI (Electromagnetic Interference) considerations

Qualifications:

• Bachelor's degree or higher in Computer Science or a related field.
• 3 - 10 years of experience.

Job Description

Location: Bangalore, India

Job Responsibilities:

• Proficiency in Layout Design and Physical Verification tools and methodologies.
• Strong understanding of Circuit Design and Analog principles.
• Experience with analog circuits and their layout techniques.
• Experience in layouts like CTLE, DFE, IDAC, PLL, LDO, BGR, TX.
• Knowledge of semiconductor design processes and industry standards.
• Attention to detail and problem-solving abilities.
• Practical experience in Serdes/DDR layout design is highly advantageous

Education & Experience:

• Bachelor's degree in Electrical Engineering, Electronics, or a related field.
• 4 - 5 years of experience on serdes/DDR layout experience. Preferably worked on TSMC 7NM, 5NM.

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is seeking a Design Verification Engineer to ensure functional correctness and robustness of mixed-signal SoC subsystems, including peripheral interfaces, audio blocks, and power management logic. You will work closely with RTL, architecture, and system teams to build comprehensive verification environments, drive coverage, and ensure first-pass silicon success.

Key Responsibilities

• Verification Architecture & Planning
  • Define and execute verification strategy for subsystems: SPI, UART, I2C, Audio interfaces (I2S, TDM), Power management digital controllers
  • Develop test plans with full functional and corner-case coverage
  • Identify verification risks and coverage gaps early
• UVM-Based Verification Development
  • Build and maintain UVM/System Verilog testbenches
  • Develop reusable VIPs and monitors, scoreboards and checkers, constrained-random stimulus
  • Implement protocol-aware verification components
• Coverage & Quality
  • Drive: functional coverage, code coverage (line, toggle, FSM)
  • Ensure closure of coverage goals and assertion checks
  • Track and report verification metrics
• Debug & Validation
  • Debug RTL issues and root-cause failures
  • Work closely with RTL engineers on bug fixes and improvements
  • Support post-silicon validation with test reuse where applicable
• System-Level Verification
  • Contribute to SoC-level verification: subsystem integration scenarios, firmware-driven tests
  • Validate interactions across clock, reset, and power domains

Required Qualifications

• 5–12 years of DV experience in SoC/subsystem verification
• Strong expertise in System Verilog and UVM
• Functional coverage and assertions (SVA)
• Experience verifying AMBA protocols (AXI/AHB/APB)
• Experience verifying peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore, India

Experience: 5–12 years

Role Overview

Skyworks is looking for a Physical Design Engineer to implement high-quality, low-power analog and digital blocks and subsystems within mixed-signal SoCs. You will be responsible for taking RTL through synthesis, place & route, and signoff, ensuring timing, power, and area targets are met. Past experience on TSMC, 22nm and below nodes. This role requires strong collaboration with RTL, DV, and analog teams to deliver silicon-ready designs.

Key Responsibilities

• Implementation Flow Ownership
  • Drive full physical design flow: Synthesis, Floorplanning, Place and route (PnR), Clock tree synthesis (CTS), Physical verification and signoff
  • Optimize for timing, power, and area (PPA)

Required Qualifications

• 5–12 years of physical design experience having worked on TSMC 22nm and below nodes
• Strong expertise in Synthesis and PnR tools (e.g., Cadence/Synopsys flows), STA and timing closure
• Experience with Advanced nodes and SoC integration, Multi-clock, multi-power domain designs

Preferred Qualifications

• Experience with mixed-signal SoC floorplanning
• Familiarity with IR drop, EM, signal integrity analysis
• Exposure to ARM Cortex-M or RISC-V based SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Hyderabad, India

Experience: 7–25 years

Key Responsibilities

Verification Architecture & Planning

• Define and execute verification strategy for subsystems:
  • SPI, UART, I2C
  • Audio interfaces (I2S, TDM)
  • Power management digital controllers
• Develop test plans with full functional and corner-case coverage
• Identify verification risks and coverage gaps early

UVM-Based Verification Development

• Build and maintain UVM/System Verilog testbenches
• Develop:
  • Reusable VIPs and monitors
  • Scoreboards and checkers
  • Constrained-random stimulus
• Implement protocol-aware verification components

Coverage & Quality

• Drive:
  • Functional coverage
  • Code coverage (line, toggle, FSM)
• Ensure closure of:
  • Coverage goals
  • Assertion checks
• Track and report verification metrics

Debug & Validation

• Debug RTL issues and root-cause failures
• Work closely with RTL engineers on bug fixes and improvements
• Support post-silicon validation with test reuse where applicable

System-Level Verification

• Contribute to SoC-level verification:
  • Subsystem integration scenarios
  • Firmware-driven tests
• Validate interactions across clock, reset, and power domains

Required Qualifications

• 7–25 years of DV experience in SoC/subsystem verification
• Strong expertise in:
  • System Verilog and UVM
  • Functional coverage and assertions (SVA)
• Experience verifying:
  • AMBA protocols (AXI/AHB/APB)
  • Peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred)

Preferred Qualifications

• Experience with mixed-signal verification environments (AMS co-sim is a plus)
• Exposure to low-power verification (UPF/CPF)
• Familiarity with ARM Cortex-M33 or RISC-V SoCs

Qualification:

• Bachelor's or Master's degree in Electronics/Electrical Engineering or related field

Job Description

Location: Bangalore

Key Responsibilities

• Own and drive DFT architecture and implementation for analog mixed signal chips from concept to production.
• Develop scan insertion, scan compression, and at-speed test strategies to meet high fault coverage and test cost targets.
• Work with cross-functional teams including design, verification, and physical design to ensure DFT integration and tapeout readiness.
• Define and implement test strategies for analog and mixed-signal IPs, including DFT hooks, wrappers, and test mode integration.
• Create test patterns and perform ATPG analysis to ensure test coverage goals are met.
• Debug DFT-related issues during silicon bring-up and collaborate with product/test engineering teams.
• Automate and optimize DFT flows and scripting for scalability and efficiency.

Required Qualifications

• B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering or related discipline.
• Minimum 10 years of hands-on experience in DFT with successful tapeouts.
• Strong knowledge of scan insertion, scan compression, transition fault (at-speed) testing, and boundary scan (IEEE 1149.1/1500).
• Proficiency in industry-standard DFT tools, with Cadence Modus experience highly desired.
• Experience with ATPG tools, test coverage analysis, and test pattern generation.
• Solid understanding of DFT for AMS blocks, including challenges in testability of analog circuits.
• Familiarity with scripting languages (TCL, Perl, Python) for automation.
• Good understanding of STA constraints for DFT and impact on synthesis and physical design.
• Proven experience in silicon debug and production test support.

Job Description

Location: Chennai

Key Responsibilities & Requirements

• Experience in Embedded firmware development.
• Experience in MISRA C, CERT C, and CWE (Common Weakness Enumeration) guidelines and making embedded firmware codebases compliant to these coding standards.
• Experience with I2C and UART is good to have.

— OR —

• Experience in Embedded firmware development with either NVMe SSD controllers (either SSD host driver or SSD device FW) or PCIe Gen4/Gen5 devices; One of these is a must.
• Experience in working with VMware ESXi environment is good to have.

Job Description

Location: Bangalore

Key Responsibilities

• Partitioning for ATPG and hierarchical approaches.
• ATPG compression and serialization.
• RTL-Scan insertion and design rule fixing.
• Expertise in Memory BIST including Memory Repair, In-System Test (IST) for Memories from Implementation to Verification and Silicon Debug.
• Experience on Boundary Scan and writing DFT mode constraints for IP's and providing the timing feedback to STA team for DFT modes.
• Experience on DFT RTL generation and Integration with RTL level QC checks like Spyglass LINT, Spyglass DFT and Fishtail.
• Familiar with IEEE1149.1, IEEE1500 and IEEE1687 standards.
• Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.
• Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis.
• Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE.
• Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE.
• Having experience with state-of-the-art, industry-standard DFT tools.
• Being hands-on from the "nitty-gritty" details to high-level planning.

Minimum Qualifications

• BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field.
• 7+ years of experience with DFT technologies, including scan test and MBIST.
• Experience with a hardware description language such as Verilog, System Verilog, or VHDL.
• Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.).
• Ability to work well in a diverse team environment.
• Experience delivering detailed technical documentation.

Job Description

Location: Santa Clara, USA

Experience: 5 - 25 years

Required Qualifications

• Bachelor's or Master's in Computer Science, Electrical Engineering, or a related field (or equivalent experience).
• 5+ years in SRE, infrastructure engineering, or systems administration.
• Strong Linux systems knowledge: networking, storage, systemd, package management, kernel parameters, and performance diagnostics.
• Hands-on experience with colocation or on-premises server infrastructure — physical hardware, rack networking, and bare-metal provisioning.
• IaC experience with Terraform and/or Ansible — writing and maintaining production configurations, not just running existing playbooks.
• Kubernetes operational experience: cluster troubleshooting, workload management, storage, and networking.
• Prometheus + Grafana or DataDog: building dashboards, writing alert rules, and understanding signal quality.
• Python and/or Bash scripting: production-quality automation, not just one-off scripts.
• Incident response experience: structured triage, RCA production, and follow-through on action items.
• Comfort operating in fast-moving startups: you own your systems, document what you build, and iterate without waiting for perfect requirements.

Strongly Preferred

• Experience operating customer-facing infrastructure or platform services with external reliability expectations.
• Cloud infrastructure operations across AWS, Azure, or GCP — including hybrid environments spanning cloud and on-prem.
• HPC job scheduler experience: Slurm, LSF, or equivalent — operations and troubleshooting.
• Knowledge of high-speed interconnect fabrics: InfiniBand, RoCE, or NVLink — configuration and troubleshooting.
• Go programming for SRE tooling — health-check services, exporters, or auto-remediation agents.
• Experience with large-scale infrastructure automation: host lifecycle management, fleet auto-healing, or AIOps-driven operations.

Job Description

Location: Bangalore

Who You'll Work With

Working as part of the hardware team. Supporting hardware and software teams with various lab activities. You will also work closely with the procurement, IT and facilities team to maintain an operational lab.

What You'll Do

Lab engineers will be responsible for hardware design and test lab upkeep, procurement, maintenance, rework and bring-up support as their primary role. They will also look after AMC for equipment and calibration of test equipment. Support any internal or external lab audits.

Key Responsibilities

• Perform rework on networking products prototypes for ICs and discrete components with high quality and reliability.
• Test and troubleshoot proto boards under Hardware lead's guidance.
• Maintain well equipped and fully functional hardware rework stations at all times.
• Coordinate the Calibration and upkeep of all lab test and measurement equipment through 3rd party or OEM.
• AMC and repair for all EDVT test chambers.
• Participate in lab audits and implement any necessary corrective actions.
• Maintain inventory of all hardware test equipment, optical modules and prototypes.
• Collaborate with IT teams to implement any required security update and ensure all lab equipment with network access compliant to IT requirements.
• Co-ordinate rework activity with 3rd party lab or CM if in-house rework is not feasible.
• Procurement of lab consumables in timely manner.
• Work with logistics co-ordinator, external test partners and facilities team to ensure SEZ compliance.
• Strict adherence to safety, industry certifications, and environmental compliance regulations.

Qualifications

• Diploma in electrical, electronics or certification course in electronics and electrical repair is preferred.
• A minimum of 7 years of experience as lab technician, or lab engineer is required.
• Ability to perform complex re-work on networking hardware is a must have skill.
• Hands-on experience of using X-ray machines, BGA rework machine is a big plus, at minimum understanding of the BGA rework process is required.
• Excellent verbal and written communication is required.
• Ability to maintain clear and traceable records for inventory with web-tool is required.
• Basic understanding of networking and ability to configure network switches, Servers is needed.

Job Description

Location: San Jose/Chandler, USA

Experience: 6 - 20 years

Position Summary

We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision.

Responsibilities

• Perform MBIST insertion for complex SoC designs using Synopsys SMS.
• Integrate and verify MBIST at the top level.
• Develop, execute, and debug MBIST simulations using Synopsys VCS, including:
  • RTL
  • No-delay gate level simulations
  • With-delay (timing-aware) simulations
• Generate and validate MBIST test patterns using Vecgen.
• Debug RTL, simulation, and MBIST integration issues.
• Support silicon bring-up, characterization, and post-silicon debug related to MBIST, memory failures, and DFT infrastructure.
• Work closely with DFT, RTL, Physical Design, and Product Engineering teams to resolve implementation issues.
• Drive issue resolution independently and document implementation flows and debug findings.

Required Qualifications

• 8+ years of hands-on DFT experience, with significant focus on MBIST.
• Strong experience with Synopsys MBIST (SMS), preferably SMS6 and/or SMS5.
• Proficiency with Synopsys VCS for MBIST verification and simulation.
• Deep understanding of the complete MBIST flow:
  • MBIST insertion
  • Top-level integration
  • Verification
  • Pattern generation (Vecgen)
  • Diagnostics
  • Simulation and debug
• Strong understanding of MBIST test algorithms (e.g., March algorithms) and memory repair schemes (BIRA/BISR, redundancy analysis, spare row/column allocation).
• Experience running and debugging:
  • No-delay simulations
  • With-delay simulations
• Experience supporting silicon bring-up, post-silicon debug, and root-cause analysis of MBIST and memory-related failures.
• Strong debugging and root-cause analysis skills across RTL, MBIST, and simulation environments.
• Ability to work independently with minimal supervision.
• Experience with large, complex SoC designs containing multiple memory instances.
• Familiarity with Verilog/SystemVerilog and standard DFT methodologies.

Preferred Qualifications

• Experience with advanced SoC DFT integration.
• Familiarity with ATPG and scan insertion flows.
• Experience with scripting (Tcl, Perl, or Python) to automate MBIST flows and debug.
• Experience working in fast-paced semiconductor product development.

Key Skills

• Synopsys MBIST (SMS5/SMS6)
• Synopsys VCS
• MBIST insertion
• Top-level MBIST verification
• VecGen pattern generation
• MBIST diagnostics
• MBIST repair schemes and memory test algorithms
• No-delay, with-delay simulation and debug
• Silicon bring-up and post-silicon debug
• SoC DFT integration
• Tcl / Perl / Python scripting
• Strong communication skills
• Self-motivated and capable of working independently

Ideal Candidate

The ideal contractor is a senior, hands-on MBIST engineer who can quickly become productive with minimal ramp-up. They should have deep experience with Synopsys SMS and VCS, excellent debugging skills, strong communication abilities, and a proven track record of independently delivering MBIST implementation, verification, and debug for complex SoC designs.

Job Description

Location: Bangalore

Experience: 5 - 7 years

Position Details

• Title/Position: Senior Embedded Engineer
• Experience: 5 to 7 Years in Embedded Software (Without Internship / Training period)
• Location: Bangalore
• Qualification: BE/Btech (EEE,EC) / ME/Mtech (EEE/EC)
• No of Position Opened: 1

Technical Skillset Required

1. Expert in Embedded C and C programming.
2. Should have strong knowledge on NON-OS, RTOS based, Linux based products development flow.
3. Hands on with peripherals drivers like I2C, SPI, UART, CAN, USB, PCIE, GPIO programming.
4. Experience in developing boot loader, bare metal low level device drivers, testing and debugging the issues.
5. Experience in UBOOT, Linux device driver and BSP configuration and development in Yocto / busybox environment.
6. Knowledge in Secure Boot, Op-TEE, Secure Debug, Security architecture includes hardware security, OS Security, Application Security.
7. Embedded domain with good experience of 32 bit microcontrollers (preferably Arm Cortex M0/M3/M4/M7).
8. Hands on with RTOS (Zephyr / FreeRTOS / VxWorks) programming with at least one project based on RTOS with any Microcontroller / Microprocessor.
9. Strong hands on debugging and troubleshooting on embedded target boards.
10. Domain knowledge in Medical, Automotive, Datacom, IOT protocols.
11. Should possess very Good Aptitude and Strong problem solving skills.

Job Description

Location: Chennai

Experience: 2 - 8 years

Job Description – Rust Configuration Tools Engineer

We are seeking a skilled Rust Configuration Tools Engineer with experience in software development to design, develop, and maintain high-performance configuration and system management tools. The ideal candidate should have strong expertise in Rust programming along with experience in embedded systems, device configuration workflows, and hardware-software integration.

Required Skills and Qualifications

• 3–7 years of experience in software development with exposure to embedded or hardware-integrated systems.
• Strong proficiency in Rust programming language.
• Familiarity with GUI frameworks or CLI tool development.
• Experience developing configuration, monitoring, or system utility tools.
• Knowledge of device communication protocols like USB, PCIe and hardware interaction.
• Familiarity with multithreading, concurrency, and performance optimization.
• Experience with Linux and/or Windows application development.
• Strong debugging and problem-solving skills.
• Experience with Git and collaborative development workflows.
• Understanding of secure coding practices and software reliability.

Job Description

Location: San Diego, USA

Experience: 2 - 7 years

Position Details

• Title: ATE Equipment/Test Technician
• Location: San Diego, CA
• Job Type: Contract
• Rate: $35-45/hr

Summary

Tessolve is hiring an ATE Equipment/Test Technician on a contract basis for our San Diego, CA location, to support handler, prober, and test station operations, including equipment troubleshooting, docking/undocking, calibration, and routine maintenance on Advantest 93K ATE systems.

About Tessolve

Tessolve is a global semiconductor engineering and test services company, providing ATE test development, product engineering, and design services to fabless and IDM customers across Digital, PMIC, RF, and Mixed Signal domains.

About the Role

As an ATE Equipment/Test Technician (Contract), you will support daily production and engineering activities by maintaining and troubleshooting handlers, probers, and test stations, performing basic ATE hardware checks, calibration, and system health checks, while collaborating with senior engineers and vendors on equipment bring-up.

What You'll Do

• Diagnose and troubleshoot handlers/probers/test stations when problems arise, working with local engineers and vendors (if needed) to bring up equipment.
• Support the setup and frequent docking/undocking of ATE to prober/handler based on daily engineering/production activities.
• Perform basic hands-on tasks on Advantest 93K ATE systems, specifically running calibration and routine maintenance.
• Perform first-level hardware checks on ATE hardware setups; complex debug is handled by senior engineers.
• Load test programs and perform basic system health checks.
• Work comfortably in a Linux environment.

What You Bring

• Technical Diploma.
• At least 3 years of experience testing semiconductors on ATE setups.
• Knowledge of basic semiconductor test processes.
• Familiarity with basic Microsoft applications.
• Comfort working in a Linux environment (required).
• Exposure to SmarTest 8 (preferred).
• Willingness to work overtime/shifts when required.
• Good interpersonal and communication skills.
• Willingness to learn and adapt.

What We Offer

• Hands-on exposure to industry-leading ATE platforms (Advantest 93K, SmarTest 8).
• Opportunity to work alongside senior engineers on equipment bring-up and production support.
• A collaborative, growth-oriented engineering culture at a global test services leader.
• Skill development in semiconductor test operations and equipment maintenance.

Job Description

Location: Dallas, USA

Experience: 2 - 7 years

Position Details

• Job Title: ATE Test Engineer - Teradyne J750
• Location: Dallas, TX USA (Onsite)
• Work Type: Fully Onsite
• Rate: $70-80/hr

Summary

Tessolve is hiring an ATE Test Engineer to join our Dallas, TX team, supporting Digital, PMIC, RF & Mixed Signal test programs on Teradyne J750 ATE platforms. This role partners directly with design engineering on first silicon bring-up, characterization, and production release.

About the Role

As an ATE Test Engineer, you will develop and debug test programs on Teradyne J750, work closely with design engineers on device characterization and test program bring-up, and support production release, yield improvement, and test time reduction initiatives.

What You'll Do

• Develop test programs for Digital, PMIC, RF & Mixed Signal products on Bench and/or ATE (Teradyne J750).
• Partner with design engineers on first silicon debug, device characterization, test program bring-up, and production release.
• Debug digital vectors (JTAG/SCAN/ATPG/Functional/Mbist) and characterize devices across PVT (Process, Voltage, Temperature).
• Characterize RF, PMIC, or Mixed Signal IP (ADC, DAC, PLL, etc.).
• Support test program hand-off, production release, yield improvement, and test time reduction initiatives.
• Collaborate closely with Product Engineering, Design Engineering, Quality Engineering, and Foundry Engineering teams.

What You Bring

• Degree in Electronics / Electrical Engineering.
• 2–7 years of relevant Test Engineering experience preferred.
• Hands-on experience with Teradyne J750 ATE (required).
• Experience using bench instrumentation for IC characterization.
• Solid knowledge of analog and digital electronics.
• Strong analytical and problem-solving skills with a hands-on lab mindset.
• Excellent verbal and written communication skills; able to work independently.
• Willingness to be based in Dallas, TX.

What We Offer

• Opportunity to work on cutting-edge Digital, PMIC, RF & Mixed Signal silicon programs.
• Direct collaboration with design and product engineering teams on first-silicon bring-up.
• Exposure to industry-leading ATE platforms (Teradyne J750).
• A collaborative, growth-oriented engineering culture at a global test services leader.

Job Description

Location: Bangalore

Experience: 8 - 15 years

We are looking for an experienced ECAD Engineer with strong hands-on experience in schematic design, constraint management, PCB reviews, and board bring-up.

Key Responsibilities

• Component selection and understanding of component datasheets/specifications.
• Schematic capture and design.
• Work closely with the ECAD/PCB team during PCB placement & routing (P&R).
• Define and manage design constraints and PCB design rules.
• Perform detailed schematic and PCB design reviews.
• Review PCB layouts for signal integrity, power, connectivity, manufacturability, etc.
• Generate and review Gerber / manufacturing files.
• Support PCB fabrication, assembly and board bring-up.
• Debug hardware issues during board bring-up and testing.
• Support validation, testing and certification activities.
• Work with cross-functional teams including hardware, ECAD, firmware and manufacturing teams.

Required Tools / Skills

• OrCAD Capture CIS – strong hands-on experience.
• Cadence Allegro PCB / Allegro PCB Reviewer – PCB review and analysis.
• Strong understanding of schematics, PCB design and constraint management.
• Understanding of PCB fabrication and manufacturing processes.
• Experience with board bring-up, debugging and testing.

Job Description

Location: Bangalore

Experience: 4 - 15 years

Job Description

We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN.

Key Responsibilities

• DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs.
• Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage.
• Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design.
• JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs.
• Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing.
• PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design.
• BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities.
• Verification: Verify DFT features and ensure their correctness through simulation and formal verification.
• Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field.
• 5 to 10 years of experience in DFT-DV engineering.
• Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG.
• Proficiency in industry-standard EDA tools for DFT implementation.
• Experience with low-power design and PHY-LP integration is a plus.
• Excellent problem-solving skills and attention to detail.
• Strong communication and teamwork skills.

Job Description

Location: Hyderabad

Experience: 5 - 13 years

Sr. Engineer II - Software QA

Mid-career Software Quality Engineer opening based in Hyderabad, India to be a key contributor in the SQA effort of PCIe, USB Driver and Ethernet Switches. In this role, you will be responsible for all aspects of quality for a family of PCIe, USB Driver and Ethernet Switches.

Responsibilities

• As a SQA engineer, work with multiple project teams internal and External development partners responsible for all stages of quality assurance for complex products and platforms, including SQA strategy, developing test plans, executing test cases, analysis, results evaluation, bug reporting and proposed corrective actions.
• Work as part of a team to develop, execute, triage, document, and test a series of features within the Switch domain under various systems to deliver a reliable and cost-effective solution.
• Understand product implementation by reading standards, functional specs, requirement specs source code and engineering discussions.
• Perform interaction with chip validation, drivers, software, design and applications teams for design details and review the Test documents.
• Reproduce, Root cause and Verify solutions to customer escalations in a timely manner.
• Provide project status and estimates and track issues to closure with project managers.
• Reviews project activities for compliance with quality assurance guidelines and standards; provides tangible feedback to improve product quality and mitigate failure risk.
• Provides domain-specific expertise and overall software quality assurance leadership and perspective to cross-organization projects, programs, and activities.
• Drives innovation and integration of new technologies into projects and activities in the software quality assurance organization.
• Understand project technical requirements, build strategy, test specification and run testcases in manual and automated mode for PCIe, NVMe applications and USB drivers.
• Sound knowledge on PCIe, NVMe and USB standards is must.
• Perform interaction with chip validation, design and applications teams for design details and review the Test documents.

Job Requirements / Qualifications

• Bachelor's degree in CSE/EEE/ECE required. Master's degree preferred.
• 7+ years of experience within PCIe, NVMe protocol and USB drivers testing.
• Experience and knowledge within network protocols, especially PCIe protocols, USB drivers, Ethernet TCP/IP and a good understanding as regards to WIN HLK test suites.
• Scripting skills in one or more of the following areas: TCL, Perl, Python and Ruby Scripting. Linux experience and Windows programming as secondary requirement.
• Protocol knowledge in many of the following areas: PCIe architecture, PHY, Transaction Layer, Non-Transparent bridge, DMA, NVMe and USB Windows/Linux drivers with strong debugging skills.
• Experience in testing PCIe functional, performance and PHY layer tests.
• Hands on experience in using with PCIe protocol exerciser and analyzer.
• Experience with test equipment like Lecroy, Viavi and Keysight exercisers and Windows HLK test suites.
• Good in English speaking and writing, excellent documentation & design specification writing skills. Must be precise and at the same time efficient in the daily work.
• Be willing to work in a changing and sometimes intense working environment.
• Solid understanding of quality assurance practices and testing methodologies.
• Very good aptitude, analytical and problem-solving skills.
• Be an energetic, creative, positive, and results-oriented Individual with emphasis on being a team player.
• Excellent communication and documentation skills.

Preferred

• Experience with PCIe, NVMe protocols and USB driver qualification.
• Experience and knowledge within network protocols, especially PCIe protocols, USB drivers, Ethernet TCP/IP and a good understanding on WIN HLK test suites.

Job Description

Location: Chandler, Hillsboro, USA

Experience: 4 - 15 years

Position Details

• Title: IC Packaging Design Engineer
• Location: Chandler, AZ or Hillsboro, OR
• Job type: Onsite
• Long Term Contract

Summary

Tessolve is hiring 4 IC Packaging Design Engineers based in Chandler, AZ (primary) or Hillsboro, OR (secondary). We're looking for senior-level talent (10+ years) primarily, with mid-level (4–6+ years MS / 6+ years BS) candidates also considered.

About the Role

As an IC Packaging Design Engineer, you'll work on physical design and layout of IC packages, driving substrate design and SI/PI-aware implementation for high-performance semiconductor products. You'll collaborate closely with cross-functional teams to ensure designs meet performance, manufacturability, yield, and reliability targets.

What You'll Do

• Perform physical design and layout of IC packages.
• Execute substrate design and layout.
• Implement SI/PI-aware design practices.
• Design for performance, manufacturability, yield, and reliability (DFM/DFY/DFR).
• Ensure design rule compliance across all deliverables.
• Use Siemens (Mentor) Xpedition (XPD) or Cadence Allegro/Advanced Package Designer (APD/SiP) for design execution.

What You Bring

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Senior-level: ~10+ years in IC packaging / package design, OR
• Mid-level: 4–6+ years (MS) or 6+ years (BS) in IC packaging / package design.
• Strong hands-on experience in Siemens Xpedition (XPD) or Cadence Allegro/APD (SiP).
• Proven experience in substrate design, SI/PI-aware implementation, and design rule compliance.

What We Offer

• Engagement with a leading semiconductor engineering firm.
• Opportunity to work on cutting-edge IC packaging projects.
• Flexible location options: Chandler, AZ or Hillsboro, OR.

About Us

Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one's intellect, skills and growth.