Job Description

Location: CA, Fremont

Experience: 3-6 Years

What you'll be doing:

• Set up x86 and SoC platforms for functional validation.
• Setting up of thermal solutions, debugger, oscilloscopes, and power measurement equipment.
• Configuring multi-boot OS with required SW, applications, tools, frameworks.
• Independently manage a group of systems to ensure stability and uninterrupted operation.
• Understand basic HW platform features - Chipset compatibility, Memory slots, expansion slots, connectivity ports, BIOS/UEFI settings.
• Basic scripting that includes modifying existing automation scripts where applicable.
• Basic understanding of different thermal solutions (e.g., air cooling, liquid cooling) and monitor temperature performance regularly - includes regular maintenance.
• Ability to configure and manage client applications on different OS environments.
• Ability to understand Client-Server workflow process and ability to analyse job logs, client logs, and test logs to identify and troubleshoot issues effectively.
• Strong troubleshooting skills to diagnose and resolve hardware, OS, and software-related issues.

Requirements:

• Diploma/B.E. with 3 years of experience in system level HW testing.
• Familiarity with assembling and testing X86/GPU based systems.
• Familiarity in executing tests under Windows and Linux environment.
• Basic knowledge on scripting and MS Excel.
• Understanding of test and measurement equipment such as oscilloscope, DAQ and DMM.
• Experience in silicon testing environment is preferred.
• Excellent organizational and documentation skills.

Job Description

Location: Bangalore, India

Experience: 3-6 Years

What you'll be doing:

• Set up x86 and SoC platforms for functional validation.
• Setting up of thermal solutions, debugger, oscilloscopes, and power measurement equipment.
• Configuring multi-boot OS with required SW, applications, tools, frameworks.
• Independently manage a group of systems to ensure stability and uninterrupted operation.
• Understand basic HW platform features - Chipset compatibility, Memory slots, expansion slots, connectivity ports, BIOS/UEFI settings.
• Basic scripting that includes modifying existing automation scripts where applicable.
• Basic understanding of different thermal solutions (e.g., air cooling, liquid cooling) and monitor temperature performance regularly - includes regular maintenance.
• Ability to configure and manage client applications on different OS environments.
• Ability to understand Client-Server workflow process and ability to analyse job logs, client logs, and test logs to identify and troubleshoot issues effectively.
• Strong troubleshooting skills to diagnose and resolve hardware, OS, and software-related issues.

Requirements:

• Diploma/B.E. with 3 years of experience in system level HW testing.
• Familiarity with assembling and testing X86/GPU based systems.
• Familiarity in executing tests under Windows and Linux environment.
• Basic knowledge on scripting and MS Excel.
• Understanding of test and measurement equipment such as oscilloscope, DAQ and DMM.
• Experience in silicon testing environment is preferred.
• Excellent organizational and documentation skills.

Job Description

Location: CA, Fremont

Experience: 2-6 Years

Description:

• Electrical validation of various IOs (PCIe, USB3, UFS, DP, HDMI, etc.) in different chips (GPU/SOC). This involves:
  • Understanding the test plan.
  • Setting up the DUT for different test cases, executing them, and recording observations for each case clearly.
  • Understanding spec expectations and flagging any failures to meet them.
  • Performing first-level triage of issues/failures (e.g., analyzing and confirming that it is an actual failure and not caused by a board, measurement setup, or other issue), followed by data collection to root-cause the failures and find a fix.

Requirements:

Educational Qualifications:

• B.E. degree with Electrical/Electronic as major subjects.

Work Experience:

• 2 to 6 years of relevant work experience.

Technical Skills:

Required:

• Clarity on signal integrity concepts (e.g., insertion loss, reflections, crosstalk, etc.).
• Clarity on signal quality parameters (e.g., eye diagram, jitter, frequency ppm, duty cycle, etc.) and how to measure them.
• Familiarity with working in a lab environment and strong knowledge of using various equipment like DSO, Multimeter, Power supplies (e.g., idea about ESD, minimum oscilloscope/probe BW required for measurement, etc.).
• Knowledge to understand board design from schematics (*.pdf file) and layout (*.brd file - using Cadence Allegro tool) (e.g., should be able to understand signal/power topology from schematics, should be able to locate test points in PCB for signal of interest, etc.).
• Knowledge to assemble an x86 motherboard (e.g., connect SMPS, DRAM cards, PCIe AIC, display, other peripherals, etc. to the x86 motherboard).
• Knowledge of board/chip bring-up flow (e.g., idea on list of items to verify before/after attaching chip to board, like verifying No-Stuff components, impedance of voltage rails, etc.).
• Proficiency in Windows & Linux OS and Microsoft Office tools (e.g., in Linux: navigate folders, edit text files, move/copy files, SSH, execute scripts, etc.).
• Familiarity with scripting languages like Python/Perl (e.g., idea about installing different python modules, execute python scripts, etc.).

Desirable:

• Knowledge and hands-on experience on high speed SERDES IO (like PCIe, USB3, UFS, Ethernet, etc.) validation (e.g., eye measurement, JTOL testing, etc.).
• Knowledge and hands-on experience of using equipment like BERT (Bit Error Ratio Tester), PCIe/USB3/UFS Logic Analyzer, etc.
• Knowledge and hands-on experience on Silicon PVT characterization.
• Knowledge and hands-on experience on board bring-up and testing.

Soft Skills:

• Be an effective team player (e.g., volunteer to take up work, own up the task and approach folks to get things done, etc.).
• Communicate observations/requirements in a crisp and straightforward way.

Other:

• Engineer should be comfortable working from the office (lab) every day (excluding holidays).

Job Description

Location: Bangalore, India

Experience: 3-7 Years

Requirements

• Development of key building blocks of memory architecture such as Row Decoder, IO, Control.
• Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing.
• Compiler level integration, verification of Compiler/Custom memories.
• Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.
• Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc.
• Good problem solving and logical reasoning skills.
• Good communication skills required.

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Requirements

• FPGA lead engineer with 8-10 yrs hands-on experience in handling FPGA design and verification.
• Should have handled RTL to bitstream design cycle on million+ gate FPGAs.
• Expertise in design partitioning, timing constraints and optimizing resource utilization.
• Should have familiarity with Intel Quartus or AMD Vivado design flows.
• Should have expertise in handling standard debugging tools such as ChipScope or custom debug tools.
• Expertise in configuring and bringing up embedded ARM cores will be an added plus.
• Expertise in FPGA based SoC emulation will also be highly beneficial.

Job Description

Location: Bangalore, India

Experience: 7-10 Years

Skills Required

• UVM, System Verilog, System C, Perl, Python, C/C++
• Protocol Knowledge - APB/AXI/CHI
• PCIE/CXL/UCIE/Ethernet
• DDR5/LPDDR5/
• JTAG/I3C/SPI
• HBM
• Arch Domain Knowledge - Processor, memory architecture, Coherency, Performance
• Tools/Flows - Questa, Visualizer
• Execute test plan and close coverage
• Write C tests
• Write SV Directed/constrained random tests
• Write Cover points, coverage closure
• Write SV Assertions
• Develop UVM, SV testbench components, complex checker, high level stimulus
• Strong debug and communication skills
• IP level verification
• PCIE/CXL/UCIE/Ethernet/DDR SubSystem Verification
• Processor verification
• Virtualization
• Coherent/non-coherent Fabric verification
• SOC verification
• Phy bring up
• UPF simulation
• Protocol Compliance Suite testing
• Gate Level Simulation

Job Description

Location: Bangalore, India

Experience: 4-6 Years

Requirements

• Develop and implement DFT infrastructure in Silicon design
• Verify DFT implementation for Correctness
• Generate test vectors, analyze and debug simulation results, improve coverage
• Deep knowledge and hands on experience with Scan insertion flows and resolving DRC
• On ChipClock controller
• Test Compression techniques
• ATPG (experience with Tessent preferred)
• Test vectors and Simulation debug

Job Description

Location: Bangalore, India

Experience: 4-8 Years

Requirements

• Clock physical design implementation and run spice simulations

Job Description

Location: Bangalore, India

Experience: 4-8 Years

Requirements

• Deep knowledge of Electromigration & IR drop concepts
• Hands on experience with Voltus (Cadence) or Redhawk(ANSYS) tools

Job Description

Location: Bangalore, India

Experience: 4-8 Years

Requirements

• Familiarity and hands-on experience with LINT, CDC, RDC, LEC + ECO implementation tools

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Requirements

• Analyze and benchmark ML systems, focusing on key performance indicators such as flop count, memory bandwidth, and memory capacity.
• Suggest improvements and optimizations to enhance overall system performance.
• Experience with performance analysis tools and methodologies, understanding of ML model architectures and computational requirements, and ability to interpret and act on complex performance data.

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Requirements

• Develop and maintain compilers specifically designed for optimizing ML models.
• This includes translating high-level ML model descriptions into efficient mapping to our hardware architecture, optimizing for performance metrics such as flop utilization, memory bandwidth, and memory capacity
• Deep understanding of ML compiler design and optimization techniques, proficiency in MLIR (multi-level Intermediate representation) and programming languages like C/C++, in-depth knowledge of ML frameworks (PyTorch) and Python.

Job Description

Location: Bangalore, India

Experience: 4-8 Years

Requirements

• Extensive experience in Linux environment
• Experience with AWS
• Experience in managing EDA applications on Cloud
• Operating Systems: Linux (Red Hat, CentOS, Ubuntu) both on premise and in AWS
• Version Control: Github (git)
• Scripting and Automation: Bash, Python, Ansible
• Applications: Jira, Confluence
• EDA Applications: Knowledge of how EDA applications work and IBM LSF or Slurm job schedulers
• Networking: TCP/IP, VLAN, DNS, Load Balancing, and security concepts, OpenVPN and tailscale Pfsense or equivalent firewalls
• Monitoring and Performance: Linux monitoring tools, Syslog
• Storage: NFS and ISCSI storage concepts

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Requirements

• Develop and optimize the runtime environment for executing ML models.
• This includes managing memory allocation, optimizing data movement, and ensuring efficient execution on targeted hardware platforms.
• Experience working with open standards like Layer Zero.
• Excellent C/C++ skills, Strong background in systems programming, experience with hardware accelerators, device drivers, proficiency with open source compiler technologies, performance profiling and debugging tools.

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Requirements

• Design ML models with an emphasis on computational efficiency and performance.
• Work closely with compiler and runtime teams to ensure models are optimized for specific hardware architectures.
• Experience developing production ML workflows, working with SOTA deployments techniques involving VectorDB and utilities like LangChain.
• Deep knowledge of ML algorithms and model architectures, experience with ML frameworks, and understanding of hardware constraints impacting model design.

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Requirements

• Design and develop the system software required to support running the ML runtime and SW stack, system initialization configuration management system, observability, and monitoring.
• Develop the hardware abstraction layer and necessary drivers.
• Deep knowledge of System HW & SW, including hands on experience with Bootstrapping flow and System Security.
• Experience in instrumenting tools and automation utilities for System Configuration and Analysis of the Observability and Monitoring trace data.

Job Description

Location: Bangalore, India

Experience: 3-5 Years

Qualification: BE (EC / equivalent)

Joining Window: Immediate – 30 days

Requirements

• Good experience in Board Bring-up, Hardware and System level debugging
• Good understanding of interfaces like DDR-2/3/4, PCIe, SerDes protocols
• Good experience on management interface like SPI, I2C
• Proven experience on preparation of Functional Specifications, Production Definition and taking ownership on Documentation
• Hands on with the usage of design tools from Mentor Graphics and Cadence
• Hands on with the usage of Digital Oscilloscope, Multimeters, test and measuring equipment

Skills

• Hands on experience on lab test equipments, MSO, DSA, spectrum analyzer, counters, signal generators, AC/DC source, E-Loads, Surge generator
• Hands-on experience on network protocol testers
• Hands-on knowledge on Freescale code warrior, Xilinx tools
• Hands-on experience on eMMC/SATA, I2C SPI bus, PCIe analyzers
• P2020, TMS320DM642 DSP, Zilog controller, PIC controllers, Network processors, 8051, 89C58, Xilinx, Altera, Atmel FPGA, CPLD, EPLD based designs.
• CPCI, Mini PCI, PCIe, USB, Ethernet, MIL1553B, JTAG,I2C, I2S, SPI, RS232, RS422
• Video and Audio interfaces, DAC, ADC, LCD
• SRAM, NAND, NOR Flash, DDR3 SDRAM, SD card Memory interfaces
• Stepper motor drive circuits, Relay control, Sensor Interface circuits, Keypad Interfaces
• Experience in EDA tools ORCAD Capture, Allegro, PADS PCB
• Design of Automated test equipment, Board test adapters.

Job Description

Location: Bangalore, India

Experience: 8-10 Years

Responsibilities

• Design and implement the backend compilers that optimize code for specialized hardware like vector processors and systolic arrays, crucial for accelerating ML workloads.
• Expertise in low-level programming and assembly language, knowledge of computer architecture, particularly vector and systolic array designs, and experience with performance tuning and analysis.
• Domain programming skills: LLVM and C/C++.

Job Description

Location: Bangalore, India

Experience: 5-7 Years

Responsibilities

• Experience and knowledge in C, development static and dynamic analysis tools, RTOS.
• Write firmware to meet the needs of the product family.

Job Description

Location: Bangalore, India

Experience: 4-6 Years

Responsibilities

• Hands-on experience with schematic tools like OrCAD.
• Expedition Designer or Concept HDL.
• Good grasp of digital electronics, power and VR design.
• Experience working with PCB layout engineers and guiding them.
• Basic knowledge of signal integrity fundamentals needed.

Job Description

Location: Bangalore, India

Experience: 4-7 Years

Qualification: BE / MTech , Electronics, IT, CS background only

Joining Window: Immediate – 30 days

Skills

• Programming: C – Mandatory
• RTOS / device drivers & Internals exposure preferably Linux – Mandatory
• Scripting exposure – Python, TCL/TL – Desirable
• Bus interface knowledge/experience: I2C, SPI, PCI/PCIE, xGMII, XAUI, UART, MDIO, etc – Mandatory (Need not be in all interface)
• Network Device driver experience
• CPU architecture: Intel (Preferred), ARM, Power-PC
• NPU Architecture: Broadcom – preferable – Qumran/Jericho family,

Job Description

Location: Bangalore, India

Experience: 4-8 Years

Requirements

• Hands-on experience with DV/DRC/LVS flows (from Cadence/Mentor) for advanced process nodes
• Define and verify Sign-off Methodology

Job Description

Location: Bangalore, India

Experience: 8+ Years

Responsibilities

• Review & Understand System level emulation plan and execute those plans seamlessly for SoC under development.
• Automate build and functional emulation tests suites wherever feasible.
• Use FPGA platform for system level emulation.
• Troubleshoot and resolve complex problems encountered while executing the system emulation test plan.
• Architect and implement protocol transactors to support FPGA stimulus.

Qualifications

• MSEE/MTECH(EE, EC, Embedded System) or BSEE/BTECH/BE(EE, EC, Embedded System) with required industry experience.
• Hands-on experience on Embedded software development with a view of system level applications of general purpose 32bit MCUs.
• Proficient in Embedded C programming.
• Able to extract high level requirements from product definition document and execute System Level Emulation.
• Has hands-on experience in using version control tool, knowledge on Git will be added advantage.
• Able to understand hardware schematic.
• Able to use Hardware tools such as logic analyzer, oscilloscope, programmer, debuggers etc.
• Knowledge on Python will be added advantage.
• Desire to learn with an aim of continuous learning.

Competencies

• Strong hands-on knowledge in Embedded C.
• Strong understanding of system level applications of general purpose 32bit MCU.
• Strong understanding of basic peripherals such as I2C, UART, SPI, Timers, ADC, DAC etc.
• Familiarization with MPLAB X IDE and Programming/Debugging Tools based on SWD/JTAG.
• Hands on experience in working on 32bit MCU, preferably with Cortex M0+/M3/M4/M7/M23/M33.
• Good understanding of Cortex M DAP and SWD interface.
• Knowledge and hands-on experience in security peripherals such as PUF, AES, ECC will be added advantage.
• Good analytical and problem-solving skills.
• Perl/python scripting languages for control of data and database environment.
• Able to communicate fluently in English language.